Compiler Researcher & Engineer
With 14 years of experience in compiler research and engineering, I specialise in analysing ISAs to understand the impact of changes on their software ecosystems. I have deep expertise in ABIs, toolchains, compilers, linkers, and libraries, and their complex interactions. I propose changes that balance performance, compatibility, security, and efficiency, and guide the implementation of early proposals through to their adoption.
My research centres on how to bring ISA improvements to existing software ecosystems, such that existing programs can take advantage of the added features. My focus is on how architectural decisions propagate through compilers, ABIs and toolchains, and how those implications can be leveraged and fed back into the architecture design process.
I have contributed extensively to Clang/LLVM, working across many layers of the compiler: the C/C++ frontend, instruction selection systems, backend passes, and assembly support. I am a core contributor to and reviewer for the RISC-V target.
My earlier research focused on solver-aided compilation, including building compilers for DSLs and intermediate representations to understand and evaluate the impact of potential optimisation techniques. I also co-authored Checked C, a C language extension to enable memory safety. My Publications page lists my publications from that time.
| I attended the RISC-V Summit North America 2025. On the member day, I gave a talk titled Toolchain Features for ISA Evolution. | |
| I wrote about LLVM 21 Improvements for Qualcomm's Platforms on the Qualcomm Open-Source blog. | |
| I attended EuroLLVM 2025. | |
| I moved to San Diego, California! | |
| I moved to the CPU Compilers team at Qualcomm. |
| I started a new role as Staff Engineer at Qualcomm. | |
| I have started a new role as a Senior Compiler Engineer at Arm. | |
| Yuichi Sugiyama, a GSoC 2020 student I helped to mentor, has written about what he accomplished this summer. Yuichi focussed on adding pointer authentication to Ibex and the RISC-V LLVM Backend. | |
| Paper: Our paper on Fireiron has been accepted to PACT 2020. | |
| I gave a guest lecture about the RISC-V ELF psABI and my work in that area to Xi Wang's Capstone Course on Operating Systems. | |
| I have been promoted to Lead Software Engineer at lowRISC. | |
| We have released a preprint describing Fireiron, a Halide-like scheduling DSL for GPU programming that I worked on while at NVIDIA. | |
| LLVM 9.0 has been released. This is the first version of LLVM which includes RISC-V as an official backend. | |
| I have written about my background in compilers and why I joined lowRISC. | |
| I have started at lowRISC, working on the LLVM RISC-V backend. | |
| A report describing a recent collaboration on Synthesizing Number Generators for Stochastic Computing using Mixed Integer Programming is now available on arXiv.org. | |
| Bravo Zulu, the yacht I raced on in Seattle until it was sold placed 7th on the Top 25 sailboats of 2018 by 48° North magazine. | |
| Paper: Our Paper, Swizzle Inventor has been accepted to ASPLOS 2019. | |
| I sailed CYC Seattle's Puget Sound Sailing Championship aboard Bravo Zulu. We came 2nd in class. This was Bravo Zulu's last regatta with that owner and crew. | |
| I joined Vinod Grover at NVIDIA, for an internship in Redmond. | |
| I sailed The Swiftsure International Yacht Race on Memorial Day Weekend, aboard Bravo Zulu. We came 28th overall in the Cape Flattery Race. | |
| Paper: Our Paper, Checked C: Making C Safe By Extension has been accepted to IEEE SecDev '18. | |
| I sailed The Southern Straits Classic Yacht Race on Easter Weekend. I was aboard Amazing Grace, a C&C 40. We came 5th in the PHRF Long Course. | |
| I attended POPL 2018 in Los Angeles! | |
| Bravo Zulu, the yacht I race on, has once again placed on the Top 25 sailboats of 2017 by 48° North magazine. This time we're 12th. | |
| I have completed my M.S. in Computer Science and Engineering at the Paul G. Allen School at the University of Washington. My Technical Report is available. | |
| I have returned to Microsoft Research for another three-month internship on the Checked C project. | |
| I have joined Microsoft Research to do a three-month internship on the Checked C project, working with David Tarditi. | |
| The yacht I race on, Bravo Zulu, placed 9th on the Top 25 sailboats of 2016 by 48° North magazine. | |
| I won the Lockheed Martin Award for Software Engineering at the Young Software Engineer of the Year Awards. | |
| I have started graduate school in Computer Science at the University of Washington, in Seattle. | |
| I attended ICFP 2015 in Vancouver. | |
| I completed my BSc (Hons) in Computer Science at the University of St Andrews, in Scotland. My BSc Dissertation is available. |
2021 Onwards I have spent the last few years researching the impact of ISA changes and extensions on compiler and toolchain design. Using my deep understanding of compiler theory, software interfaces, and ISA design, I analyse proposed ISA changes, model their compatibility and performance implications, and translate findings into concrete toolchain improvements.
I have done this kind of analysis for both RISC-V ISA extensions and for Arm Architecture extensions. My results feed directly back into the ISA design process.
This work also involves collaborating with researchers and practitioners across the software ecosystem, to define standards and their implementations, and to guide improvements. My research has guided teams that implement improvements to compilers, assemblers, linkers, libraries and other tools.
I am a member of RISC-V International and the RISE project, where I serve on several relevant committees.
2017 Onwards My major focus for the last several years has been working on LLVM-based projects.
I am a member of Qualcomm's CPU Compilers team. My work is included in Qualcomm's Snapdragon LLVM compiler and their open-source CPU LLVM toolchain.
I am a major contributor to and reviewer for the RISC-V target in LLVM. I am a significant reviewer of changes to the RISC-V backend in LLVM.
At Arm I was a member of the Arm Compiler for Embedded team, which maintained a proprietary LLVM-based toolchain for embedded ARM CPUs, including the official Arm Architecture assembler. I was also involved in the team's work to ensure that upstream LLVM support for the Arm Architecture was complete and well-maintained.
At lowRISC I worked on the RISC-V target, from frontend improvements to backend bugfixes, including coordinating contributions from the team there. I also occasionally contribute RISC-V related improvements to the Rust compiler.
2019 Onwards I am a leading expert in the RISC-V ELF psABI, which I contribute to as part of my work at both Qualcomm and lowRISC. I have also contributed to other relevant RISC-V software specifications for toolchains, compilers and linkers.
I defined Qualcomm's extensions to the RISC-V psABI, which add novel relocations and linker relaxations to enable the use of Qualcomm's RISC-V ISA extensions.
I maintain a list of ABI-related resources on GitHub, which may be useful to others.
2018 I worked on how solvers and synthesis can be used to create (or assist in creating) Halide-like schedules for linear algebra applications. The requirement that the structure of these schedules be amenable to synthesis fed into the Fireiron work, a system for scheduling dense linear algebra algorithms on GPUs.
2018 I worked on using program synthesis techniques to assist programmers in designing efficient data access patterns for parallel programs.
"Swizzle Inventor: Data Movement Synthesis for GPU Kernels" Paper →
2017 I worked at Microsoft Research on a project to make C safer, by adding bounds checks to memory accesses. This included design of low-cost dynamic checks as well as bounds inference algorithms.
2014–2015 My bachelor's dissertation project was producing an Idris to Erlang compiler, and associated libraries for producing verified concurrent programs in Idris that use Erlang VM features.
2013–2014 I worked on the data types team at Basho, developing novel CRDTs that are included in Riak since version 2.0.
"Riak DT Map: a Composable, Convergent Replicated Dictionary" Workshop Paper →
"CRDTs: An Update (or just a PUT)" Talk at RICON West 2013 →
2012 I worked at the University of St Andrews on the ParaPhrase project to develop parallel skeleton library for Erlang.
“Cost-Directed Refactoring of Parallel Erlang Programs” Journal Paper →
I have sailed most of my life, and in 2016 I got hooked on yacht racing.